#ifndef INC__CHIP_DEFS_H__
#define INC__CHIP_DEFS_H__

//Chip type rule:
//First number   1: M0   4: M4   5: NUC505 or others
//Second number - page size  M0(0: 512B,  1: 1KB,  2: 2KB)   M4(0: 2KB,  1:4KB)
typedef enum
{
	NUC_CHIP_TYPE_GENERAL_V6M	= 0,
	NUC_CHIP_TYPE_NUC1XX		= 1,
	NUC_CHIP_TYPE_N572			= 2,
	NUC_CHIP_TYPE_M05X			= 3,
	NUC_CHIP_TYPE_GENERAL_ARM7	= 4,
	NUC_CHIP_TYPE_GENERAL_ARM9	= 5,
	NUC_CHIP_TYPE_GENERAL_855	= 6,
	NUC_CHIP_TYPE_GENERAL_82J	= 7,
	NUC_CHIP_TYPE_GENERAL_83J	= 8,
	NUC_CHIP_TYPE_GENERAL_35J	= 9,
	NUC_CHIP_TYPE_GENERAL_87J	= 10,
	NUC_CHIP_TYPE_GENERAL_21J	= 11,
	NUC_CHIP_TYPE_GENERAL_658	= 12,
	NUC_CHIP_TYPE_GENERAL_659	= 13,
	NUC_CHIP_TYPE_GENERAL_1T	= 14,
	NUC_CHIP_TYPE_NANO100		= 0x101,
	NUC_CHIP_TYPE_MINI51		= 0x102,
	NUC_CHIP_TYPE_MT5XX			= 0x103,
	NUC_CHIP_TYPE_N570			= 0x104,
	NUC_CHIP_TYPE_AU91XX		= 0x114,
	NUC_CHIP_TYPE_NM1120		= 0x105,
	NUC_CHIP_TYPE_M0564			= 0x121,
	NUC_CHIP_TYPE_GENERAL_V7M	= 0x400,
	NUC_CHIP_TYPE_NUC4XX		= 0x401,
	NUC_CHIP_TYPE_M451			= 0x402,
	NUC_CHIP_TYPE_TC8226		= 0x411,
	NUC_CHIP_TYPE_NUC505		= 0x500
} NUC_CHIP_TYPE_E;

extern NUC_CHIP_TYPE_E g_eChipType;

#define ARM_SRAM_START_ADDRESS			0x20000000

/* Offline flash information defined by USB dongle */
#define NUC_OFFLINE_FLASH_ADDR			0x00000000UL
#define NUC_OFFLINE_FLASH_PAGE_SIZE		256
#define NUC_OFFLINE_FLASH_SIZE			(512*1024)

/* Chip definition for NUC1xx */
#define NUC1XX_FLASH_LDROM_ADDR			0x00100000UL
#define NUC1XX_FLASH_APROM_ADDR			0x00000000UL
#define NUC1XX_FLASH_NVM_ADDR			0x0001F000UL
#define NUC1XX_FLASH_CONFIG_ADDR		0x00300000UL
#define NUC1XX_FLASH_LDROM_SIZE			4096
#define NUC1XX_FLASH_NVM_SIZE			4096
#define NUC1XX_FLASH_CONFIG_SIZE		8
#define NUC1XX_FLASH_PAGE_SIZE			512
#define NUC1XX_RAM_START_ADDR			0x20000000UL
#define NUC1XX_RAM_MIN_SIZE				2048
#define NUC1XX_RAM_MAX_SIZE				0x4000UL

#define NUC1XX_FLASH_CONFIG_CWDTEN		0x80000000UL
#define NUC1XX_FLASH_CONFIG_CWDTEN_BIT1		0x00000010UL
#define NUC1XX_FLASH_CONFIG_CWDTEN_BIT0		0x00000008UL
#define NUC1XX_FLASH_CONFIG_CWDTPDEN		0x40000000UL
#define NUC1XX_FLASH_CONFIG_CGPFMFP		0x08000000UL
#define NUC1XX_FLASH_CONFIG_CKF			0x10000000UL
#define NUC1XX_FLASH_CONFIG_CFOSC		0x07000000UL
#	define NUC1XX_FLASH_CONFIG_E12M		0x00000000UL
#	define NUC1XX_FLASH_CONFIG_E32K		0x01000000UL
#	define NUC1XX_FLASH_CONFIG_PLL		0x02000000UL
#	define NUC1XX_FLASH_CONFIG_I10K		0x03000000UL
#	define NUC1XX_FLASH_CONFIG_I22M		0x04000000UL
#define NUC1XX_FLASH_CONFIG_CBODEN		0x00800000UL
#define NUC1XX_FLASH_CONFIG_CBOV		0x00600000UL
#	define NUC1XX_FLASH_CONFIG_CBOV_45	0x00600000UL
#	define NUC1XX_FLASH_CONFIG_CBOV_38	0x00400000UL
#	define NUC1XX_FLASH_CONFIG_CBOV_26	0x00200000UL //2.6/2.7V
#	define NUC1XX_FLASH_CONFIG_CBOV_22	0x00000000UL
#define NUC1XX_FLASH_CONFIG_CBORST		0x00100000UL
#define NUC1XX_FLASH_CONFIG_CIOINI		0x00000400UL
#	define NUC1XX_FLASH_CONFIG_CIOINI_INPUT	0x00000000UL
#	define NUC1XX_FLASH_CONFIG_CIOINI_BI	0x00000400UL
#define NUC1XX_FLASH_CONFIG_CBS			0x00000080UL
#define NUC1XX_FLASH_CONFIG_CBS2		0x000000C0UL
/* Boot from APROM, LDROM invisible */
#	define NUC1XX_FLASH_CONFIG_CBS_AP			0x000000C0UL
/* Boot from LDROM, APROM invisible */
#	define NUC1XX_FLASH_CONFIG_CBS_LD			0x00000040UL
/* Boot from APROM, LDROM visible */
#	define NUC1XX_FLASH_CONFIG_CBS_AP_LD		0x00000080UL
/* Boot from LDROM, APROM visible */
#	define NUC1XX_FLASH_CONFIG_CBS_LD_AP		0x00000000UL
#define NUC1XX_FLASH_CONFIG_DFVSEN		0x00000004UL
#define NUC1XX_FLASH_CONFIG_LOCK		0x00000002UL
#define NUC1XX_FLASH_CONFIG_DFEN		0x00000001UL
#define NUC1XX_FLASH_CONFIG_DFBA		0x0001FE00UL

#define M0519_FLASH_LDROM_SIZE			8192
#define MT5XX_REG_PID					0x50000000UL
#define MT5XX_FLASH_CONFIG_CHZ_BPWM		0x00001000UL
#define MT5XX_FLASH_CONFIG_CHZ_Odd1		0x00000800UL
#define MT5XX_FLASH_CONFIG_CHZ_Event1	0x00000400UL
#define MT5XX_FLASH_CONFIG_CHZ_Odd0		0x00000200UL
#define MT5XX_FLASH_CONFIG_CHZ_Event0	0x00000100UL

/* Chip definition for AU91xx */
#define AU91XX_FLASH_LDROM_ADDR			0x00100000UL
#define AU91XX_FLASH_APROM_ADDR			0x00000000UL
#define AU91XX_FLASH_LDROM_SIZE			4096
#define AU91XX_FLASH_CONFIG_ADDR		0x00300000UL
#define AU91XX_FLASH_CONFIG_SIZE		8
#define AU91XX_FLASH_PAGE_SIZE			1024
#define AU91XX_RAM_START_ADDR			0x20000000UL
#define AU91XX_RAM_MIN_SIZE				0x1000UL
#define AU91XX_RAM_MAX_SIZE				0x3000UL

#define AU91XX_FLASH_CONFIG_CBODEN		0x00800000UL
#define AU91XX_FLASH_CONFIG_CBS			0x00000080UL
#define AU91XX_FLASH_CONFIG_LDROM_EN	0x00000004UL
#define AU91XX_FLASH_CONFIG_LOCK		0x00000002UL
#define AU91XX_FLASH_CONFIG_DFEN		0x00000001UL
#define AU91XX_FLASH_CONFIG_DFBA		0x0003FC00UL

/* Chip definition for M05x */
#define M05X_FLASH_LDROM_ADDR			0x00100000UL
#define M05X_FLASH_APROM_ADDR			0x00000000UL
#define M05X_FLASH_NVM_ADDR				0x0001F000UL
#define M05X_FLASH_CONFIG_ADDR			0x00300000UL
#define M05X_FLASH_LDROM_SIZE			4096
#define M05X_FLASH_NVM_SIZE				4096
#define M05X_FLASH_CONFIG_SIZE			8
#define M05X_FLASH_PAGE_SIZE			512
#define M05X_RAM_START_ADDR				0x20000000UL
#define M05X_RAM_MIN_SIZE				2048

#define M05X_FLASH_CONFIG_CWDTEN		0x80000000UL
#define M05X_FLASH_CONFIG_CWDTPDEN		0x40000000UL
#define M05X_FLASH_CONFIG_CKF			0x10000000UL
#define M05X_FLASH_CONFIG_CGP7MFP		0x08000000UL
#define M05X_FLASH_CONFIG_CFOSC			0x07000000UL
#	define M05X_FLASH_CONFIG_E12M		0x00000000UL
#	define M05X_FLASH_CONFIG_E32K		0x01000000UL
#	define M05X_FLASH_CONFIG_PLL		0x02000000UL
#	define M05X_FLASH_CONFIG_I10K		0x03000000UL
#	define M05X_FLASH_CONFIG_I22M		0x04000000UL
#define M05X_FLASH_CONFIG_CBODEN		0x00800000UL
#define M05X_FLASH_CONFIG_CBOV			0x00600000UL
#	define M05X_FLASH_CONFIG_CBOV_45	0x00600000UL
#	define M05X_FLASH_CONFIG_CBOV_38	0x00400000UL
#	define M05X_FLASH_CONFIG_CBOV_26	0x00200000UL
#	define M05X_FLASH_CONFIG_CBOV_22	0x00000000UL
#define M05X_FLASH_CONFIG_CBORST		0x00100000UL
#define M05X_FLASH_CONFIG_CIOINI		0x00000400UL
#	define M05X_FLASH_CONFIG_CIOINI_INPUT	0x00000000UL
#	define M05X_FLASH_CONFIG_CIOINI_BI		0x00000400UL
#define M05X_FLASH_CONFIG_CBS2			0x000000C0UL
/* Boot from APROM, LDROM invisible */
#	define M05X_FLASH_CONFIG_CBS_AP			0x000000C0UL
/* Boot from LDROM, APROM invisible */
#	define M05X_FLASH_CONFIG_CBS_LD			0x00000040UL
/* Boot from APROM, LDROM visible */
#	define M05X_FLASH_CONFIG_CBS_AP_LD		0x00000080UL
/* Boot from LDROM, APROM visible */
#	define M05X_FLASH_CONFIG_CBS_LD_AP		0x00000000UL
#define M05X_FLASH_CONFIG_CBS			0x00000080UL
#define M05X_FLASH_CONFIG_LOCK			0x00000002UL
#define M05X_FLASH_CONFIG_DFEN			0x00000001UL
#define M05X_FLASH_CONFIG_DFBA			0x000FFFFFUL

/* Chip definition for Nano100 */
#define NANO100_FLASH_LDROM_ADDR		0x00100000UL
#define NANO100_FLASH_APROM_ADDR		0x00000000UL
#define NANO100_FLASH_NVM_ADDR			0x0001F000UL
#define NANO112_FLASH_SPROM_ADDR		0x00200000UL
#define NANO100_FLASH_CONFIG_ADDR		0x00300000UL
#define NANO103_FLASH_KPROM_ADDR		0x00301000UL
#define NANO100_FLASH_LDROM_SIZE		4096
#define NANO103_FLASH_LDROM_SIZE		4096
#define NANO100_FLASH_NVM_SIZE			4096
#define NANO112_FLASH_SPROM_SIZE		512
#define NANO100_FLASH_CONFIG_SIZE		8
#define NANO103_FLASH_KPROM_SIZE		1024
#define NANO100_FLASH_PAGE_SIZE			512
#define NANO100_RAM_START_ADDR			0x20000000UL
#define NANO100_RAM_MIN_SIZE			2048

#define NANO100_FLASH_CONFIG_CWDTEN		0x80000000UL
#define NANO100_FLASH_CONFIG_CKF		0x10000000UL
#define NANO100_FLASH_CONFIG_CFOSC		0x04000000UL
#	define NANO100_FLASH_CONFIG_E12M	0x00000000UL
#	define NANO100_FLASH_CONFIG_I12M	0x04000000UL
#define NANO100_FLASH_CONFIG_CBORST		0x00180000UL
#	define NANO100_FLASH_CONFIG_CBORST_RESERVED	0x00180000UL
#	define NANO100_FLASH_CONFIG_CBORST_25		0x00100000UL
#	define NANO100_FLASH_CONFIG_CBORST_20		0x00080000UL
#	define NANO100_FLASH_CONFIG_CBORST_17		0x00000000UL
#define NANO103_FLASH_CONFIG_CBORST				0x00780000UL	//NANO103
#	define NANO103_FLASH_CONFIG_CBORST_RESERVED	0x00000000UL
#	define NANO103_FLASH_CONFIG_CBORST_18		0x00080000UL
#	define NANO103_FLASH_CONFIG_CBORST_19		0x00100000UL
#	define NANO103_FLASH_CONFIG_CBORST_20		0x00180000UL
#	define NANO103_FLASH_CONFIG_CBORST_21		0x00200000UL
#	define NANO103_FLASH_CONFIG_CBORST_22		0x00280000UL
#	define NANO103_FLASH_CONFIG_CBORST_23		0x00300000UL
#	define NANO103_FLASH_CONFIG_CBORST_24		0x00380000UL
#	define NANO103_FLASH_CONFIG_CBORST_25		0x00400000UL
#	define NANO103_FLASH_CONFIG_CBORST_26		0x00480000UL
#	define NANO103_FLASH_CONFIG_CBORST_27		0x00500000UL
#	define NANO103_FLASH_CONFIG_CBORST_28		0x00580000UL
#	define NANO103_FLASH_CONFIG_CBORST_29		0x00600000UL
#	define NANO103_FLASH_CONFIG_CBORST_30		0x00680000UL
#	define NANO103_FLASH_CONFIG_CBORST_31		0x00780000UL
#define NANO103_FLASH_CONFIG_CBODEN				0x00800000UL
#define NANO100_FLASH_CONFIG_CBS				0x000000C0UL
/* Boot from APROM, LDROM invisible */
#	define NANO100_FLASH_CONFIG_CBS_AP			0x000000C0UL
/* Boot from LDROM, APROM invisible */
#	define NANO100_FLASH_CONFIG_CBS_LD			0x00000040UL
/* Boot from APROM, LDROM visible */
#	define NANO100_FLASH_CONFIG_CBS_AP_LD		0x00000080UL
/* Boot from LDROM, APROM visible */
#	define NANO100_FLASH_CONFIG_CBS_LD_AP		0x00000000UL
#define NANO100_FLASH_CONFIG_HXT_GAIN			0x0000E000UL	//NANO112
#	define NANO100_FLASH_CONFIG_HXT_RESERVED	0x00000000UL
#	define NANO100_FLASH_CONFIG_HXT_H16			0x00002000UL
//#	define NANO100_FLASH_CONFIG_HXT_12_16		0x00004000UL
#	define NANO100_FLASH_CONFIG_HXT_12_16		0x0000E000UL
#	define NANO100_FLASH_CONFIG_HXT_8_12		0x00006000UL
#	define NANO100_FLASH_CONFIG_HXT_L8			0x00008000UL
#define NANO103_FLASH_CONFIG_HXT_GAIN			0x0000E000UL	//NANO103
#	define NANO103_FLASH_CONFIG_HXT_RESERVED	0x00000000UL
#	define NANO103_FLASH_CONFIG_HXT_4			0x00002000UL
#	define NANO103_FLASH_CONFIG_HXT_H8			0x00004000UL
#	define NANO103_FLASH_CONFIG_HXT_H12			0x00006000UL
#	define NANO103_FLASH_CONFIG_HXT_H16			0x00008000UL
#	define NANO103_FLASH_CONFIG_HXT_H24			0x0000A000UL
#	define NANO103_FLASH_CONFIG_HXT_H32			0x0000E000UL
#define NANO100_FLASH_CONFIG_CCKSTOP			0x00001000UL
#define NANO100_FLASH_CONFIG_MERASE				0x00000020UL
#define NANO100_FLASH_CONFIG_LOCK		0x00000002UL
#define NANO100_FLASH_CONFIG_DFEN		0x00000001UL
#define NANO100_FLASH_CONFIG_DFBA		0x0000FE00UL	//NANO100 AN
#define NANO100_FLASH_CONFIG_DFBA_BN	0x0001EA00UL	//NANO100 BN
#define NANO112_FLASH_CONFIG_DFBA		0x00007E00UL	//NANO112

/* Chip definition for Mini51 */
#define MINI51_FLASH_LDROM_ADDR			0x00100000UL
#define MINI51_FLASH_APROM_ADDR			0x00000000UL
#define MINI51_FLASH_CONFIG_ADDR		0x00300000UL
#define MINI51_FLASH_LDROM_SIZE			2048
#define MINI51_FLASH_CONFIG_SIZE		8
#define MINI51_FLASH_PAGE_SIZE			512
#define MINI51_RAM_START_ADDR			0x20000000UL
#define MINI51_RAM_MIN_SIZE				2048

#define MINI51_FLASH_CONFIG_PWM_EVEN	0x40000000UL
#define MINI51_FLASH_CONFIG_PWM_ODD		0x20000000UL
#define MINI51_FLASH_CONFIG_CKF			0x10000000UL
#define MINI51_FLASH_CONFIG_CBOD2VEN	0x00800000UL
#define MINI51_FLASH_CONFIG_CBOV		0x00600000UL
#	define MINI51_FLASH_CONFIG_CBOV_DISABLE	0x00600000UL
#	define MINI51_FLASH_CONFIG_CBOV_44		0x00600000UL
#	define MINI51_FLASH_CONFIG_CBOV_38		0x00400000UL //3.8/3.7V
#	define MINI51_FLASH_CONFIG_CBOV_27		0x00200000UL
#	define MINI51_FLASH_CONFIG_CBOV_27_		0x00000000UL
#	define MINI51_FLASH_CONFIG_CBOV_22		0x00000000UL
#define MINI51_FLASH_CONFIG_CBOV2		0x00080000UL
#	define MINI51_FLASH_CONFIG_CBOVE_30	(~MINI51_FLASH_CONFIG_CBOD2VEN & (MINI51_FLASH_CONFIG_CBOV2 | (0x3 << 21)))
#	define MINI51_FLASH_CONFIG_CBOVE_24	(~MINI51_FLASH_CONFIG_CBOD2VEN & (MINI51_FLASH_CONFIG_CBOV2 | (0x2 << 21)))
#	define MINI51_FLASH_CONFIG_CBOVE_20	(~MINI51_FLASH_CONFIG_CBOD2VEN & (MINI51_FLASH_CONFIG_CBOV2 | (0x1 << 21)))
#	define MINI51_FLASH_CONFIG_CBOVE_17	(~MINI51_FLASH_CONFIG_CBOD2VEN & (MINI51_FLASH_CONFIG_CBOV2 | (0x0 << 21)))
#	define MINI51_FLASH_CONFIG_CBOVE_43	(~MINI51_FLASH_CONFIG_CBOD2VEN & ~MINI51_FLASH_CONFIG_CBOV2 & (0x3 << 21))
#	define MINI51_FLASH_CONFIG_CBOVE_37	(~MINI51_FLASH_CONFIG_CBOD2VEN & ~MINI51_FLASH_CONFIG_CBOV2 & (0x2 << 21))
#	define MINI51_FLASH_CONFIG_CBOVE_27	(~MINI51_FLASH_CONFIG_CBOD2VEN & ~MINI51_FLASH_CONFIG_CBOV2 & (0x1 << 21))
#	define MINI51_FLASH_CONFIG_CBOVE_22	(~MINI51_FLASH_CONFIG_CBOD2VEN & ~MINI51_FLASH_CONFIG_CBOV2 & (0x0 << 21))
#define MINI51_FLASH_CONFIG_CBORST		0x00100000UL
#define MINI51_FLASH_CONFIG_RCCLK_D2	0x00008000UL
#define MINI51_FLASH_CONFIG_CIOINI		0x00000400UL
#define MINI51_FLASH_CONFIG_RCTRIM_S	0x08000000UL
#define MINI51_FLASH_CONFIG_CBS2		0x000000C0UL
/* Boot from APROM, LDROM invisible */
#	define MINI51_FLASH_CONFIG_CBS_AP			0x000000C0UL
/* Boot from LDROM, APROM invisible */
#	define MINI51_FLASH_CONFIG_CBS_LD			0x00000040UL
/* Boot from APROM, LDROM visible */
#	define MINI51_FLASH_CONFIG_CBS_AP_LD		0x00000080UL
/* Boot from LDROM, APROM visible */
#	define MINI51_FLASH_CONFIG_CBS_LD_AP		0x00000000UL
#define MINI51_FLASH_CONFIG_CBS			0x00000080UL
#define MINI51_FLASH_CONFIG_LOCK		0x00000002UL
#define MINI51_FLASH_CONFIG_DFEN		0x00000001UL
//#define MINI51_FLASH_CONFIG_DFBA		0x00003E00UL
#define MINI51_FLASH_CONFIG_DFBA		0x00007E00UL //17.5/32K

#define NUC121_FLASH_LDROM_SIZE			4608	//4.5K

/* Chip definition for NM1120 */
#define NM1120_FLASH_SPROM_ADDR			0x00200000UL
#define NM1120_FLASH_SPROM2_ADDR		0x00240000UL
#define NM1120_FLASH_SPROM3_ADDR		0x00280000UL
#define NM1120_FLASH_CONFIG_ADDR		0x00300000UL
#define NM1120_FLASH_LDROM_SIZE			2048
#define NM1120_FLASH_SPROM_SIZE			512
#define NM1120_FLASH_CONFIG_SIZE		8
#define NM1120_FLASH_CONFIG_CBOV		0x0000E000UL
#	define NM1120_FLASH_CONFIG_CBOV_43		0x0000E000UL
#	define NM1120_FLASH_CONFIG_CBOV_40		0x0000C000UL
#	define NM1120_FLASH_CONFIG_CBOV_37		0x0000A000UL
#	define NM1120_FLASH_CONFIG_CBOV_30		0x00008000UL
#	define NM1120_FLASH_CONFIG_CBOV_27		0x00006000UL
#	define NM1120_FLASH_CONFIG_CBOV_24		0x00004000UL
#	define NM1120_FLASH_CONFIG_CBOV_22		0x00002000UL
#	define NM1120_FLASH_CONFIG_CBOV_20		0x00000000UL
#define NM1120_FLASH_CONFIG_GPA0NIRI		0x00030000UL
#define NM1120_FLASH_CONFIG_GPA1NIRI		0x000C0000UL
#define NM1120_FLASH_CONFIG_GPA2NIRI		0x00300000UL
#define NM1120_FLASH_CONFIG_GPA3NIRI		0x00C00000UL
#define NM1120_FLASH_CONFIG_GPA4NIRI		0x03000000UL
#define NM1120_FLASH_CONFIG_GPA5NIRI		0x0C000000UL
#define NM1120_FLASH_CONFIG_CKFHIRC		0x20000000UL
#define NM1120_FLASH_CONFIG_CBORST		0x00001000UL
#define NM1120_FLASH_CONFIG_CBOVEN		0x00000800UL
#define NM1120_FLASH_CONFIG_CIOINI		0x00000400UL
#define NM1120_FLASH_CONFIG_CBS			0x000000C0UL
/* Boot from APROM, LDROM invisible */
#	define NM1120_FLASH_CONFIG_CBS_AP			0x000000C0UL
/* Boot from LDROM, APROM invisible */
#	define NM1120_FLASH_CONFIG_CBS_LD			0x00000040UL
/* Boot from APROM, LDROM visible */
#	define NM1120_FLASH_CONFIG_CBS_AP_LD		0x00000080UL
/* Boot from LDROM, APROM visible */
#	define NM1120_FLASH_CONFIG_CBS_LD_AP		0x00000000UL
#define NM1120_FLASH_CONFIG_PWM_DBGEN	0x00000004UL
#define NM1120_FLASH_CONFIG_LOCK		0x00000002UL
#define NM1120_FLASH_CONFIG_DFEN		0x00000001UL
#define NM1120_FLASH_CONFIG_DFBA		0x00007E00UL
#define NM1120_FLASH_PAGE_SIZE			512
#define NM1120_RAM_START_ADDR			0x20000000UL
#define NM1120_RAM_MIN_SIZE				2048

/* Chip definition for N570 */
#define N570_FLASH_CONFIG_CBOV			0x03C00000UL
#	define N570_FLASH_CONFIG_CBOV_46	0x03C00000UL
#	define N570_FLASH_CONFIG_CBOV_42	0x03800000UL
#	define N570_FLASH_CONFIG_CBOV_39	0x03400000UL
#	define N570_FLASH_CONFIG_CBOV_37	0x03000000UL
#	define N570_FLASH_CONFIG_CBOV_36	0x02C00000UL
#	define N570_FLASH_CONFIG_CBOV_34	0x02800000UL
#	define N570_FLASH_CONFIG_CBOV_31	0x02400000UL
#	define N570_FLASH_CONFIG_CBOV_30	0x02000000UL
#	define N570_FLASH_CONFIG_CBOV_28	0x01C00000UL
#	define N570_FLASH_CONFIG_CBOV_26	0x01800000UL
#	define N570_FLASH_CONFIG_CBOV_24	0x01400000UL
#	define N570_FLASH_CONFIG_CBOV_22	0x01000000UL
#	define N570_FLASH_CONFIG_CBOV_21	0x00C00000UL
#	define N570_FLASH_CONFIG_CBOV_20	0x00800000UL
#	define N570_FLASH_CONFIG_CBOV_19	0x00400000UL
#	define N570_FLASH_CONFIG_CBOV_18	0x00000000UL
#define N570_FLASH_CONFIG_CLVR			0x08000000UL
#define N570_FLASH_CONFIG_CBHYS			0x04000000UL
#define N570_FLASH_CONFIG_CBORST		0x00200000UL
#define N570_FLASH_CONFIG_CBOVEN		0x00100000UL
#define N570_FLASH_CONFIG_CBS			0x00000080UL
#define N570_FLASH_CONFIG_LOCK			0x00000002UL
#define N570_FLASH_CONFIG_DFEN			0x00000001UL

/* Chip definition for N572 */
#define N572_FLASH_APROM_ADDR			0x00000000UL
#define N572_FLASH_APROM_SIZE			0x00010000UL
#define N572_FLASH_CONFIG_ADDR			0x00300000UL
#define N572_FLASH_CONFIG_SIZE			20
#define N572_FLASH_PAGE_SIZE			512
#define N572_RAM_START_ADDR				0x20000000UL
#define N572_RAM_MIN_SIZE				4096

#define N572_FLASH_CONFIG_CWDTEN		0x80000000UL
#define N572_FLASH_CONFIG_CKF			0x10000000UL
#define N572_FLASH_CONFIG_CFOSC			0x07000000UL
#	define N572_FLASH_CONFIG_E12M6M		0x01000000UL
#	define N572_FLASH_CONFIG_I24M		0x07000000UL
#define N572_FLASH_CONFIG_CVDEN			0x00800000UL
#define N572_FLASH_CONFIG_CVDTV			0x00200000UL
#define N572_FLASH_CONFIG_LOCK			0x00000002UL
#define N572_PROTECT_8K_FLASH			0x00000004UL

/* Chip definition for NUC4xx */
#define NUC4XX_FLASH_LDROM_ADDR			0x00100000UL
#define NUC4XX_FLASH_APROM_ADDR			0x00000000UL
#define NUC4XX_FLASH_NVM_ADDR			0x0001F000UL
#define NUC4XX_FLASH_UHB_ADDR			0x00200000UL // UHB is abbreviated from User Hidden Block
#define NUC4XX_FLASH_SK_ADDR			0x00200800UL
#define NUC4XX_FLASH_CONFIG_ADDR		0x00300000UL
#define NUC4XX_FLASH_LDROM_SIZE			0x4000
#define NUC4XX_FLASH_NVM_SIZE			0x4000
#define NUC4XX_FLASH_UHB_SIZE			0x800		 // from DrvFMC.h. It is different from the FMC spec. I guess it includes the Super Key Block so as to be larger than 0x400 shown in the Spec.
#define NUC4XX_FLASH_CONFIG_SIZE		16
#define NUC4XX_FLASH_PAGE_SIZE			2048
#define NUC4XX_FLASH_PAGE_ERASE_SIZE	2048
#define NUC4XX_FLASH_PAGE_PROG_SIZE	    2048         // ? or 512 depended on ICP Tool
#define NUC4XX_FLASH_MULTI_PROG_SIZE	16           // ? 512 if in time
#define NUC4XX_RAM_START_ADDR			0x20000000UL
#define NUC4XX_RAM_MIN_SIZE				0x4000UL
#define NUC4XX_RAM_MAX_SIZE				0x10000UL    // Depended on NuLink-M4

#define NUC4XX_FLASH_CONFIG_CWDTEN		0x80000000UL
#define NUC4XX_FLASH_CONFIG_CWDTPDEN	0x40000000UL
#define NUC4XX_FLASH_CONFIG_CGPFMFP		0x08000000UL
#define NUC4XX_FLASH_CONFIG_CKF			0x10000000UL
#define NUC4XX_FLASH_CONFIG_CFOSC		0x07000000UL
#	define NUC4XX_FLASH_CONFIG_E12M		0x00000000UL
#	define NUC4XX_FLASH_CONFIG_E32K		0x01000000UL
#	define NUC4XX_FLASH_CONFIG_PLL		0x02000000UL
#	define NUC4XX_FLASH_CONFIG_I10K		0x03000000UL
#	define NUC4XX_FLASH_CONFIG_I22M		0x04000000UL
#define NUC4XX_FLASH_CONFIG_CBODEN		0x00800000UL
#define NUC4XX_FLASH_CONFIG_CBOV		0x00600000UL
#	define NUC4XX_FLASH_CONFIG_CBOV_45	0x00600000UL
#	define NUC4XX_FLASH_CONFIG_CBOV_38	0x00400000UL
#	define NUC4XX_FLASH_CONFIG_CBOV_26	0x00200000UL
#	define NUC4XX_FLASH_CONFIG_CBOV_22	0x00000000UL
#define NUC4XX_FLASH_CONFIG_CBORST		0x00100000UL
#define NUC4XX_FLASH_CONFIG_RMII		0x00008000UL
#define NUC4XX_FLASH_CONFIG_CFG32K		0x00004000UL
#define NUC4XX_FLASH_CONFIG_LDWPEN		0x00000800UL
#define NUC4XX_FLASH_CONFIG_CIOINI		0x00000400UL
#define NUC4XX_FLASH_CONFIG_CBS			0x00000080UL
#define NUC4XX_FLASH_CONFIG_CBS2		0x000000C0UL
/* Boot from APROM, LDROM invisible */
#	define NUC4XX_FLASH_CONFIG_CBS_AP			0x000000C0UL
/* Boot from LDROM, APROM invisible */
#	define NUC4XX_FLASH_CONFIG_CBS_LD			0x00000040UL
/* Boot from APROM, LDROM visible */
#	define NUC4XX_FLASH_CONFIG_CBS_AP_LD		0x00000080UL
/* Boot from LDROM, APROM visible */
#	define NUC4XX_FLASH_CONFIG_CBS_LD_AP		0x00000000UL
#define NUC4XX_FLASH_CONFIG_DFVSEN		0x00000004UL
#define NUC4XX_FLASH_CONFIG_LOCK		0x00000002UL
#define NUC4XX_FLASH_CONFIG_DFEN		0x00000001UL
#define NUC4XX_FLASH_CONFIG_DFBA		0x0007F800UL

/* Chip definition for M451 */
#define M451_FLASH_LDROM_ADDR			0x00100000UL
#define M451_FLASH_APROM_ADDR			0x00000000UL
#define M451_FLASH_NVM_ADDR				0x0001F000UL
#define M451_FLASH_SPROM_ADDR			0x00200000UL
#define M451_FLASH_UHB_ADDR				0x00200000UL // UHB is abbreviated from User Hidden Block
#define M451_FLASH_SK_ADDR				0x00200800UL
#define M451_FLASH_CONFIG_ADDR			0x00300000UL
#define M451_FLASH_LDROM_SIZE			0x1000
#define M451_FLASH_NVM_SIZE				0x1000
#define M451_FLASH_SPROM_SIZE			0x800
#define M451_FLASH_UHB_SIZE				0x800        // from DrvFMC.h. It is different from the FMC spec. I guess it includes the Super Key Block so as to be larger than 0x400 shown in the Spec.
#define M451_FLASH_CONFIG_SIZE			8
#define M451_FLASH_PAGE_SIZE			2048
#define M451_FLASH_PAGE_ERASE_SIZE		2048
#define M451_FLASH_PAGE_PROG_SIZE		2048         // ? or 512 depended on ICP Tool
#define M451_FLASH_MULTI_PROG_SIZE		16           // ? 512 if in time

#define M451_FLASH_CONFIG_CWDTEN		0x80000000UL
#define M451_FLASH_CONFIG_CWDTEN_BIT1		0x00000010UL
#define M451_FLASH_CONFIG_CWDTEN_BIT0		0x00000008UL
#define M451_FLASH_CONFIG_CWDTPDEN		0x40000000UL
#define M451_FLASH_CONFIG_CGPFMFP		0x08000000UL
#define M451_FLASH_CONFIG_CFOSC			0x04000000UL
#	define M451_FLASH_CONFIG_E12M		0x00000000UL
#	define M451_FLASH_CONFIG_I22M		0x04000000UL
#define M451_FLASH_CONFIG_CBODEN		0x00800000UL
#define M451_FLASH_CONFIG_CBOV			0x00600000UL
#	define M451_FLASH_CONFIG_CBOV_45	0x00600000UL
#	define M451_FLASH_CONFIG_CBOV_38	0x00400000UL
#	define M451_FLASH_CONFIG_CBOV_26	0x00200000UL
#	define M451_FLASH_CONFIG_CBOV_22	0x00000000UL
#define M451_FLASH_CONFIG_CBORST		0x00100000UL
#define M451_FLASH_CONFIG_XT1TYP		0x00010000UL //not release in TRM
#	define M451_FLASH_CONFIG_XT1TYP_INV		0x00000000UL
#	define M451_FLASH_CONFIG_XT1TYP_GM		0x00010000UL
#define M451_FLASH_CONFIG_CIOINI		0x00000400UL
#define M451_FLASH_CONFIG_CBS			0x00000080UL
#define M451_FLASH_CONFIG_CBS2			0x000000E0UL
/* Boot from APROM, LDROM invisible */
#	define M451_FLASH_CONFIG_CBS_AP		0x000000E0UL
/* Boot from LDROM, APROM invisible */
#	define M451_FLASH_CONFIG_CBS_LD		0x00000060UL
/* Boot from APROM, LDROM visible */
#	define M451_FLASH_CONFIG_CBS_AP_LD	0x000000A0UL
/* Boot from LDROM, APROM visible */
#	define M451_FLASH_CONFIG_CBS_LD_AP	0x00000020UL
#	define M451_FLASH_CONFIG_CBS_MK		0x000000C0UL
#define M451_FLASH_CONFIG_DFVSEN		0x00000004UL
#define M451_FLASH_CONFIG_LOCK			0x00000002UL
#define M451_FLASH_CONFIG_DFEN			0x00000001UL
#define M451_FLASH_CONFIG_DFBA			0x0003F800UL

#define NUC505_SPIFLASH_PAGE_SIZE		256
#define NUC505_SPIFLASH_SECTOR_SIZE		4096
#define NUC505_MAX_RAM_SIZE				0x20000

#define TC8226_FLASH_KPROM_ADDR			0x00301000UL
#define TC8226_FLASH_KPROM_SIZE			0x2000
#define TC8226_FLASH_PAGE_SIZE			0x1000
#define TC8226_FLASH_CONFIG_CWDTEN		0x80000000UL
#define TC8226_FLASH_CONFIG_CWDTEN_BIT1		0x00000010UL
#define TC8226_FLASH_CONFIG_CWDTEN_BIT0		0x00000008UL
#define TC8226_FLASH_CONFIG_CWDTPDEN		0x40000000UL
#define TC8226_FLASH_CONFIG_CGPFMFP		0x08000000UL
#define TC8226_FLASH_CONFIG_CFOSC			0x04000000UL
#	define TC8226_FLASH_CONFIG_E12M		0x00000000UL
#	define TC8226_FLASH_CONFIG_I22M		0x04000000UL
#define TC8226_FLASH_CONFIG_CBODEN		0x00080000UL
#define TC8226_FLASH_CONFIG_CBOV		0x00E00000UL
#	define TC8226_FLASH_CONFIG_CBOV_16		0x00000000UL
#	define TC8226_FLASH_CONFIG_CBOV_18		0x00200000UL
#	define TC8226_FLASH_CONFIG_CBOV_20		0x00400000UL
#	define TC8226_FLASH_CONFIG_CBOV_22		0x00600000UL
#	define TC8226_FLASH_CONFIG_CBOV_24		0x00800000UL
#	define TC8226_FLASH_CONFIG_CBOV_26		0x00A00000UL
#	define TC8226_FLASH_CONFIG_CBOV_28		0x00C00000UL
#	define TC8226_FLASH_CONFIG_CBOV_30		0x00E00000UL
#define TC8226_FLASH_CONFIG_CBORST		0x00100000UL
#define TC8226_FLASH_CONFIG_XT1TYP		0x00010000UL //not release in TRM
#	define TC8226_FLASH_CONFIG_XT1TYP_INV		0x00000000UL
#	define TC8226_FLASH_CONFIG_XT1TYP_GM		0x00010000UL
#define TC8226_FLASH_CONFIG_CIOINI		0x00000400UL
#define TC8226_FLASH_CONFIG_CBS			0x00000080UL
#define TC8226_FLASH_CONFIG_CBS2			0x000000E0UL
/* Boot from APROM, LDROM invisible */
#	define TC8226_FLASH_CONFIG_CBS_AP		0x000000E0UL
/* Boot from LDROM, APROM invisible */
#	define TC8226_FLASH_CONFIG_CBS_LD		0x00000060UL
/* Boot from APROM, LDROM visible */
#	define TC8226_FLASH_CONFIG_CBS_AP_LD	0x000000A0UL
/* Boot from LDROM, APROM visible */
#	define TC8226_FLASH_CONFIG_CBS_LD_AP	0x00000020UL
#	define TC8226_FLASH_CONFIG_CBS_MK		0x000000C0UL
#define TC8226_FLASH_CONFIG_DFVSEN		0x00000004UL
#define TC8226_FLASH_CONFIG_LOCK			0x00000002UL
#define TC8226_FLASH_CONFIG_DFEN			0x00000001UL
#define TC8226_FLASH_CONFIG_DFBA			0x0003F800UL
#define TC8226_FLASH_CONFIG_MERASE			0x00002000UL
#define TC8226_FLASH_CONFIG_SPLCAEN			0x00001000UL

#define NUMICRO_M0_FLASH_APROM_ADDR		0x00000000UL
#define NUMICRO_M0_FLASH_LDROM_ADDR		0x00100000UL
#define NUMICRO_M0_FLASH_SPROM_ADDR		0x00200000UL
#define NUMICRO_M0_FLASH_CONFIG_ADDR	0x00300000UL
#define NUMICRO_M0_FLASH_PAGE_SIZE		512

#define NUMICRO_M4_FLASH_APROM_ADDR		0x00000000UL
#define NUMICRO_M4_FLASH_LDROM_ADDR		0x00100000UL
#define NUMICRO_M4_FLASH_SPROM_ADDR		0x00200000UL
#define NUMICRO_M4_FLASH_CONFIG_ADDR	0x00300000UL



/* 8051 1T Series */
#define N76E1T_FLASH_CONFIG_ADDR		0x30000
#define N76E1T_FLASH_CONFIG_SIZE		8
#define N76E1T_FLASH_CONFIG_LOCK		0x02
#define N76E1T_FLASH_SECTOR_SIZE		128
#define N76E1T_FLASH_SECTOR_SIZE_616	256
#define N76E1T_FLASH_PAGE_SIZE			32

#endif
